With increases in circuit speed and miniaturization of ICs, parasitic effects become the bottleneck of IC performance. The RC time constant becomes the dominate part in controlling the performance of IC circuits, especially microprocessors. There are two different paths to controlling the contribution of parasitic effects.
The first path is to control the passive parasitic effects in interconnect systems which form connections to the source, gate, and drain electrodes. In such interconnect systems, metal connections are made by multilayer interconnects supported over the substrate by an interlayer dielectric. To control passive parasitic effects in interconnect systems, technologists have proposed to use low dielectric constant materials such as SiOF, BN, polyimides, Teflon.TM., BCB (benzocyclobutene), and other spin-on materials as the dielectric, so that the conductor-to-conductor coupling is minimized. Others have proposed to use low-resistance interconnect systems based on low resistance conductors such as copper, gold, etc. Still others have proposed to use "pseudo-low dielectric constant technology", i.e., exchange complexity for relaxed design rules such that more metal interconnect layers are used and each layer can use less aggressive design rules; see patent application Ser. No. 08/330,767, filed on Oct. 28, 1994, by R. W. Cheung entitled "Pseudo-low Dielectric Constant Technology", now U.S. Pat. No. 5,471,093 issued Nov. 28, 1995.
The second option for controlling the contribution of parasitic effects in integrated circuits is to control the active capacitance. Some technologists have proposed to lower the active capacitance, i.e., minimize the overlap capacitance of the transistor by reducing the Miller capacitance. The LDD (lightly doped drain) approach is one proposed technology that can minimize Miller capacitance. Others have proposed a "Raised Source-Drain" technology for minimizing the source-drain area and hence reducing the capacitance.
In addition to controlling parasitic effects, low-resistance interconnect systems are useful in other applications. In particular, there is also a need for low resistance local interconnects for some applications in SRAM (static random access memory) technology. With the advance of local interconnect (LI) technology, one can optimize the cell size of the SRAM core cell and provide highly competitive SRAM technologies. Accordingly, some technologists have proposed "amorphous Si LI" technology comprising Si/Ti interconnect structures. Others have proposed "Stable LI technology" comprising Si/Ti/TiN/Ti interconnect structures, see, e.g., patent application Ser. No. 08/309,692, filed on Sep. 21, 1994, by S. Kamaswami et al entitled "A Stable Local Interconnect/Active Area Silicide Structure for VLSI Applications", now U.S. Pat. No. 5,451,545 issued Sep. 19, 1995. Still others have proposed TiN as the LI structure.
All the proposed interconnect systems discussed above can provide some relief to technology requirements in one form or another; however, none provide a comprehensive solution. Accordingly, there remains a need for such comprehensive solution.